The present invention relates to a semiconductor integrated circuit and, for example, to a semiconductor integrated circuit that can be used under several voltage conditions.
For example, an output voltage of a semiconductor integrated circuit that is mounted on an SD card is defined as either 1.8V or 3.3V by the SD card specification. Therefore, a semiconductor integrated circuit capable of generating output voltages at both voltage levels has been developed recently.
Generally, a semiconductor integrated circuit capable of generating both output voltage levels is configured using MOS transistors with a thick gate oxide film so as to withstand a high voltage condition (3.3V).
However, a semiconductor integrated circuit that is configured using MOS transistors with a thick gate oxide film has a problem of a lower operating speed and a larger circuit size. Thus, a semiconductor integrated circuit needs to be configured using MOS transistors with a gate oxide film that is as thin as possible in order to improve the operating speed and prevent an increase in circuit size.
A related art is disclosed in Japanese Patent No. 3530315. According to an output circuit (semiconductor integrated circuit) disclosed in Japanese Patent No. 3530315, even when a power supply voltage of an external LSI is higher than a withstand voltage of a gate oxide film of MOS transistors, the semiconductor output circuit outputs a signal with an amplitude of the power supply voltage of the external LSI without applying a voltage higher than the withstand voltage to the gate oxide film of each MOS transistor.
Further, according to the semiconductor output circuit, in the case where a second voltage VDD2 is equal to or lower than a first voltage VDD1 (which is under a low voltage condition), a bypass path is formed to thereby reduce the delay time when generating an output voltage of H level.